Toshinori Sato

ORCID

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 37

Top Venues

CoRR

ISOCC

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

ISDCS

Publications

Tomoya Mizumoto, Takato Yamazaki, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato
Dialogue Systems Can Generate Appropriate Responses without the Use of Question Marks?- a Study of the Effects of "?" for Spoken Dialogue Systems -. LREC/COLING (2024)
Yui Koyanagi, Tomoaki Ukezono, Toshinori Sato
A Light-weight and Tamper-resistant AES Implementation by FPGAs. ISCAS (2024)
Shun Kiyono, Sho Takase, Shengzhe Li, Toshinori Sato
Bridging the Gap between Subword and Character Segmentation in Pretrained Language Models. RANLP (2023)
Hiroyuki Hama, Tomoaki Ukezono, Toshinori Sato
Negative Impact of Approximated Signed Addition on Power Reduction. ISDCS (2023)
Tatsuya Ide, Eiki Murata, Daisuke Kawahara, Takato Yamazaki, Shengzhe Li, Kenta Shinzato, Toshinori Sato
PHALM: Building a Knowledge Graph from Scratch by Prompting Humans and a Language Model. CoRR (2023)
Toshiki Kawamoto, Yuki Okano, Takato Yamazaki, Toshinori Sato, Kotaro Funakoshi, Manabu Okumura
A Follow-up Study on Evaluation Metrics Using Follow-up Utterances. PACLIC (2023)
Takato Yamazaki, Tomoya Mizumoto, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato
An Open-Domain Avatar Chatbot by Exploiting a Large Language Model. SIGDIAL (2023)
Takato Yamazaki, Katsumasa Yoshikawa, Toshiki Kawamoto, Tomoya Mizumoto, Masaya Ohagi, Toshinori Sato
Building a hospitable and reliable dialogue system for android robots: a scenario-based approach with large language models. Adv. Robotics 37 (21) (2023)
Hiroyuki Hama, Tomoaki Ukezono, Toshinori Sato
Leveraging Approximate Computing for IoT Image Transmission. ISOCC (2023)
Tomoya Mizumoto, Takato Yamazaki, Katsumasa Yoshikawa, Masaya Ohagi, Toshiki Kawamoto, Toshinori Sato
Dialogue Systems Can Generate Appropriate Responses without the Use of Question Marks? - Investigation of the Effects of Question Marks on Dialogue Systems. CoRR (2023)
Hiroyuki Hama, Toshinori Sato
Towards At-the-Edge ECG Signal Processing with Accuracy-tunable Approximate Adders. GCCE (2023)
Toshinori Sato, Hiroyuki Hama, Tomoaki Ukezono
Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition. ISOCC (2023)
Tomohito Kasahara, Daisuke Kawahara, Nguyen Tung, Shengzhe Li, Kenta Shinzato, Toshinori Sato
Building a Personalized Dialogue System with Prompt-Tuning. NAACL-HLT (Student Research Workshop) (2022)
Takato Yamazaki, Katsumasa Yoshikawa, Toshiki Kawamoto, Masaya Ohagi, Tomoya Mizumoto, Shuta Ichimura, Yusuke Kida, Toshinori Sato
Tourist Guidance Robot Based on HyperCLOVA. CoRR (2022)
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge. ACM Great Lakes Symposium on VLSI (2022)
Masaki Sano, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
An Accuracy-Controllable Approximate Adder for FPGAs. ATAIT (2022)
Tomohito Kasahara, Daisuke Kawahara, Nguyen Tung, Shengzhe Li, Kenta Shinzato, Toshinori Sato
Building a Personalized Dialogue System with Prompt-Tuning. CoRR (2022)
Toshinori Sato, Tomoaki Ukezono
A Dynamically Configurable Approximate Array Multiplier with Exact Mode. ICCCS (2020)
Toshinori Sato, Tomoaki Ukezono
Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2020)
Tongxin Yang, Toshinori Sato, Tomoaki Ukezono
An Accuracy-Configurable Adder for Low-Power Applications. IEICE Trans. Electron. (3) (2020)
Toshinori Sato, Tomoaki Ukezono
On Applications of Configurable Approximation to Irregular Voltage. NORCAS (2019)
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method. ACM Great Lakes Symposium on VLSI (2019)
Tongxin Yang, Toshinori Sato, Tomoaki Ukezono
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area. ISVLSI (2019)
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
Design and Analysis of Approximate Multipliers with a Tree Compressor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2019)
Toshinori Sato, Tomoaki Ukezono
Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance. PRDC (2019)
Toshinori Sato, Tomoaki Ukezono
Correcting Sign Calculation Errors in Configurable Approximations. APCCAS (2019)
Tongxin Yang, Toshinori Sato, Tomoaki Ukezono
A Low-Power Approximate Multiply-Add Unit. ISDCS (2019)
Toshinori Sato, Tongxin Yang, Tomoaki Ukezono
Trading Accuracy for Power with a Configurable Approximate Adder. IEICE Trans. Electron. (4) (2019)
Toshinori Sato, Tomoaki Ukezono
Tolerating Aging-Induced Timing Violations Via Configurable Approximations. GCCE (2019)
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
A Low-Power Yet High-Speed Configurable Adder for Approximate Computing. ISCAS (2018)
Toshinori Sato, Tomoaki Ukezono
Exploiting Configurability for Correct Sign Calculation in an Approximate Adder. ISOCC (2018)
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
A low-power configurable adder for approximate applications. ISQED (2018)
Hiroyuki Baba, Tongxin Yang, Masahiro Inoue, Kaori Tajima, Tomoaki Ukezono, Toshinori Sato
A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing. ISVLSI (2018)
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
A low-power high-speed accuracy-controllable approximate multiplier design. ASP-DAC (2018)
Ryuta Ishida, Toshinori Sato, Tomoaki Ukezono
Approximate Adder Generation for Image Processing Using Convolutional Neural Network. ISOCC (2018)
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor. ICCD (2017)
Ken Yano, Takanori Hayashida, Toshinori Sato
Improving timing error tolerance without impact on chip area and power consumption. ISQED (2013)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida
A Selective Replacement Method for Timing-Error-Predicting flip-Flops. J. Circuits Syst. Comput. 21 (6) (2012)
Toshinori Sato, Hideki Mori, Rikiya Yano, Takanori Hayashida
Importance of Single-Core Performance in the Multicore Era. ACSC (2012)
Alex Veidenbaum, Nectarios Koziris, Toshinori Sato, Avi Mendelson
Topic 4: High-Performance Architecture and Compilers. Euro-Par (2012)
Toshinori Sato, Takanori Hayashida, Ken Yano
Dynamically reducing overestimated design margin of MultiCores. HPCS (2012)
Ken Yano, Takanori Hayashida, Toshinori Sato
Analysis of SER Improvement by Radiation Hardened Latches. PRDC (2012)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida
Guidelines for mitigating NBTI degradation in on-chip memories. ISCIT (2012)
Toshinori Sato, Takahito Yoshiki, Takanori Hayashida
Multicore Power Management Utilizing Error-Predicting Flip-flop. CISIS (2011)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI. IEICE Trans. Electron. (4) (2011)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
Signal probability control for relieving NBTI in SRAM cells. ISQED (2010)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
A Replacement Strategy for Canary Flip-Flops. PRDC (2010)
Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura
Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. IEICE Trans. Electron. (4) (2009)
Toshinori Sato, Shingo Watanabe
Uncriticality-directed scheduling for tackling variation and power challenges. ISQED (2009)
Shingo Watanabe, Masanori Hashimoto, Toshinori Sato
A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED (2009)
Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato
A Low-Power Instruction Issue Queue for Microprocessors. IEICE Trans. Electron. (4) (2008)
Toshinori Sato, Toshimasa Funaki
Dependability, power, and performance trade-off on a multicore processor. ASP-DAC (2008)
Toshinori Sato, Shingo Watanabe
Instruction Scheduling for Variation-Originated Variable Latencies. ISQED (2008)
Toshinori Sato
A Simple Mechanism for Collapsing Instructions under Timing Speculation. IEICE Trans. Electron. (9) (2008)
Toshimasa Funaki, Toshinori Sato
Formulating MITF for a Multicore Processor with SEU Tolerance. DSD (2008)
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP (2008)
Shingo Watanabe, Toshinori Sato
Uncriticality-Directed Low-Power Instruction Scheduling. ISVLSI (2008)
Toshinori Sato, Yuji Kunitake
Exploiting Input Variations for Energy Reduction. PATMOS (2007)
Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato
Challenges in Evaluations for a Typical-Case Design Methodology. ISQED (2007)
Toshinori Sato, Yuji Kunitake
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM. ISQED (2007)
Kenji Kise, Toshinori Sato, Hironori Nakajo
Introduction. SIGARCH Comput. Archit. News 35 (5) (2007)
Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato
Indirect Tag Search Mechanism for Instruction Window Energy Reduction. CIT (2007)
Toshinori Sato, Toshimasa Funaki
Power-Performance Trade-Off of a Dependable Multicore Processor. PRDC (2007)
Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu
Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism. Int. J. Comput. Their Appl. 14 (2) (2007)
Akihiro Chiyonobu, Toshinori Sato
Energy-efficient instruction scheduling utilizing cache miss information. SIGARCH Comput. Archit. News 34 (1) (2006)
Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu
Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors. PATMOS (2006)
Toshinori Sato, Akihiro Chiyonobu
Evaluating the Impact of Fault Recovery on Superscalar Processor Performance. PRDC (2006)
Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato
A leakage-energy-reduction technique for cache memories in embedded processors. J. Embed. Comput. 2 (1) (2006)
Takamasa Tokunaga, Toshinori Sato
Profiling with Helper Threads. Parallel and Distributed Computing and Networks (2005)
Yuichiro Imaizumi, Toshinori Sato
Folding Active List for High Performance and Low Power. ISHPC (2005)
Toshinori Sato, Akihiro Chiyonobu
An Energy-Efficient Clustered Superscalar Processor. IEICE Trans. Electron. (4) (2005)
Toshinori Sato
Exploiting Trivial Computation in Dependable Processors. CATA (2005)
Yuu Tanaka, Toshinori Sato, Takenori Koushiro
The potential in energy efficiency of a speculative chip-multiprocessor. SPAA (2004)
Akihiro Chiyonobu, Toshinori Sato
Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture. ISICT (2004)
Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato
A leakage-energy-reduction technique for highly-associative caches in embedded systems. SIGARCH Comput. Archit. News 32 (3) (2004)
Masaharu Goto, Toshinori Sato
Leakage Energy Reduction in Register Renaming. ICDCS Workshops (2004)
Seiichiro Fujii, Toshinori Sato
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors. EUC (2004)
Hidenori Sato, Toshinori Sato
A static and dynamic energy reduction technique for I-cache and BTB in embedded processors. ASP-DAC (2004)
Toshinori Sato
Exploiting Instruction Redundancy for Transient Fault Tolerance. DFT (2003)
Takenori Koushiro, Toshinori Sato, Itsujiro Arita
A trace-level value predictor for Contrail processors. SIGARCH Comput. Archit. News 31 (3) (2003)
Toshinori Sato, Itsujiro Arita
Combining variable latency pipeline with instruction reuse for execution latency reduction. Systems and Computers in Japan 34 (12) (2003)
Akihito Sakanaka, Toshinori Sato
Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction. PATMOS (2003)
Toshinori Sato, Daisuke Morishita
A field-customizable and runtime-adaptable microarchitecture. FPT (2003)
Asami Tanino, Toshinori Sato
Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation. CAINE (2003)
Toshinori Sato, Itsujiro Arita
Low-Cost Value Predictors Using Frequent Value Locality. ISHPC (2002)
Toshinori Sato, Itsujiro Arita
Reducing Energy Consumption via Low-Cost Value Prediction. PATMOS (2002)
Toshinori Sato
Evaluating the impact of reissued instructions on data speculative processor performance. Microprocess. Microsystems 25 (9-10) (2002)
Toshinori Sato, Kiichi Sugitani, Akihiko Hamano
Evaluating Influence of Compiler Optimizations on Data Speculation. J. Inf. Sci. Eng. 18 (6) (2002)
Toshinori Sato, Itsujiro Arita
Simplifying Instruction Issue Logic in Superscalar Processors. DSD (2002)
Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita
The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization. PDPTA (2002)
Toshinori Sato, Itsujiro Arita
In Search of Efficient Reliable Processor Design. ICPP (2001)
Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita
Influence of Compiler Optimizations on Value Prediction. HPCN Europe (2001)
Toshinori Sato, Itsujiro Arita
Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications. PRDC (2001)
Toshinori Sato, Itsujiro Arita
Tolerating Transient Faults through an Instruction Reissue Mechanism. PDCS (2001)
Toshinori Sato, Itsujiro Arita
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse. Euro-Par (2001)
Toshinori Sato, Itsujiro Arita
Partial Resolution in Data Value Predictors. ICPP (2000)
Toshinori Sato, Itsujiro Arita
Comprehensive Evaluation of an Instruction Reissue Mechanism. ISPAN (2000)
Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu
300MHz design methodology of VU for emotion synthesis. ASP-DAC (2000)
Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing. IEEE J. Solid State Circuits 35 (7) (2000)

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Publication Activity (10 Years)

Top Topics

Top Venues

Toshinori Sato