Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture.
Akihiro ChiyonobuToshinori SatoPublished in: ISICT (2004)
Keyphrases
- low power
- functional units
- high speed
- processing elements
- power consumption
- single chip
- low cost
- vlsi architecture
- gate array
- cmos technology
- real time
- finite state machines
- image processing algorithms
- nm technology
- massively parallel
- hardware implementation
- image processing
- random access
- parallel architecture
- vlsi implementation
- logic circuits
- associative memory
- low power consumption
- mixed signal
- parallel processors
- hardware architecture
- frame rate