Improving timing error tolerance without impact on chip area and power consumption.
Ken YanoTakanori HayashidaToshinori SatoPublished in: ISQED (2013)
Keyphrases
- power consumption
- error tolerance
- low power
- dynamic power management
- power dissipation
- low power consumption
- nm technology
- cmos technology
- power management
- single chip
- power saving
- energy efficiency
- low cost
- high speed
- power reduction
- energy saving
- battery life
- image sensor
- battery powered
- image processing
- clock frequency
- data center
- sensor networks