Barry Shackleford

Publication Activity (10 Years)

Years Active: 1997-2002
Publications (10 Years): 0

Publications

Barry Shackleford, Motoo Tanaka, Richard J. Carter, Greg Snider
Random Number Generators Implemented with Neighborhood-of-Four, Non-locally Connected Cellular Automata. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Barry Shackleford, Motoo Tanaka, Richard J. Carter, Greg Snider
FPGA implementation of neighborhood-of-four cellular automata random number generators. FPGA (2002)
Barry Shackleford, Motoo Tanaka, Richard J. Carter, Greg Snider
High-Performance Cellular Automata Random Number Generators for Embedded Probabilistic Computing Systems. Evolvable Hardware (2002)
Barry Shackleford, Greg Snider, Richard J. Carter, Etsuko Okushi, Mitsuhiro Yasuda, Katsuhiko Seo, Hiroto Yasuura
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. Genet. Program. Evolvable Mach. 2 (1) (2001)
Greg Snider, Barry Shackleford, Richard J. Carter
Attacking the semantic gap between application programming languages and configurable hardware. FPGA (2001)
Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
An FPGA-based genetic algorithm machine (poster abstract). FPGA (2000)
Mitsuhiro Yasuda, Katsuhiko Seo, Hisao Koizumi, Barry Shackleford, Fumio Suzuki
A Top-down Hardware/Software Co-Simulation Method for Embedded Systems Based Upon a Component Logical Bus Architecture. ASP-DAC (1998)
Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm. ICONIP (1) (1997)
Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura
Memory-CPU Size Optimization for Embedded System Designs. DAC (1997)