Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams.
Masahiro FujitaYusuke MatsunagaTakeo KakudaPublished in: ICCAD (1990)
Keyphrases
- temporal logic
- model checking
- binary decision diagrams
- symbolic model checking
- modal logic
- satisfiability problem
- boolean functions
- belief revision
- formal specification
- linear temporal logic
- computation tree logic
- model checker
- finite state
- transition systems
- automata theoretic
- formal specification language
- formal verification
- temporally extended
- state space
- general purpose