How-Rern Lin

Publication Activity (10 Years)

Years Active: 1994-2010
Publications (10 Years): 0

Publications

Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. ASP-DAC (2010)
Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
How-Rern Lin, Wei-Hao Chiu, Tsung-Yi Wu
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates. IEICE Trans. Electron. (4) (2009)
How-Rern Lin, TingTing Hwang
On determining sensitization criterion in an iterative gate sizing process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (2) (1999)
How-Rern Lin, Yu-Chin Hsu, TingTing Hwang
Cell height driven transistor sizing in a cell based static CMOS module design. IEEE J. Solid State Circuits 31 (5) (1996)
How-Rern Lin, TingTing Hwang
Power recduction by gate sizing with path-oriented slack calculation. ASP-DAC (1995)
How-Rern Lin, TingTing Hwang
Dynamical identification of critical paths for iterative gate sizing. ICCAD (1994)
How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang
Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC (1994)