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Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs.

Tsung-Yi WuTzi-Wei KaoShi-Yi HuangTai-Lun LiHow-Rern Lin
Published in: ASP-DAC (2010)
Keyphrases
  • edge detection
  • high speed
  • image quality
  • low power
  • edge information