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Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs.
Tsung-Yi Wu
Tzi-Wei Kao
How-Rern Lin
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2010)
Keyphrases
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edge detection
reduction method
image segmentation
low power
weighted graph
multi processor