Jia Yu

Publication Activity (10 Years)

Years Active: 2004-2012
Publications (10 Years): 0

Top Topics

Network Topologies

Computational Model

Top Venues

Publications

Bin Liu, Bo Yuan, Huichen Dai, Hongbo Zhao, Jia Yu, Laxmi N. Bhuyan
Improving the throughput and delay performance of network processors by applying push model. IWQoS (2012)
Bo Yuan, Hongbo Zhao, Chengchen Hu, Bin Liu, Jia Yu, Laxmi N. Bhuyan
Experience on Applying Push Model to Packet Processors in High Performance Routers. GLOBECOM (2010)
Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. Bhuyan
Revisiting the Cache Effect on Multicore Multithreaded Network Processors. DSD (2008)
Jia Yu, Jingnan Yao, Laxmi N. Bhuyan, Jun Yang
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining. DAC (2007)
Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan
Conserving network processor power consumption by exploiting traffic variability. ACM Trans. Archit. Code Optim. 4 (1) (2007)
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
Assertion-Based Design Exploration of DVS in Network Processor Architectures CoRR (2007)
Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan
Enhancing Network Processor Simulation Speed with Statistical Input Sampling. HiPEAC (2005)
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE (2005)
Jun Yang, Jia Yu, Youtao Zhang
A low energy cache design for multimedia applications exploiting set access locality. J. Syst. Archit. 51 (10-11) (2005)
Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan
Low power network processor design using clock gating. DAC (2005)
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
Assertion-based power/performance analysis of network processor architectures. HLDVT (2004)