Low power network processor design using clock gating.
Yan LuoJia YuJun YangLaxmi N. BhuyanPublished in: DAC (2005)
Keyphrases
- low power
- single chip
- power consumption
- power reduction
- power dissipation
- high speed
- gate array
- low cost
- low power consumption
- logic circuits
- clock gating
- vlsi architecture
- power saving
- digital signal processing
- cmos technology
- vlsi circuits
- energy efficiency
- communication networks
- network structure
- power management
- image processing
- design process
- mixed signal