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23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.

Tah-Kang Joseph TingGyh-Bin WangMing-Hung WangChun-Peng WuChun-Kai WangChun-Wei LoLi-Chin TienDer-Min YuanYung-Ching HsiehJenn-Shiang LaiWen-Pin HsuChien-Chih HuangChi-Kang ChenYung-Fa ChouDing-Ming KwaiZhe WangWei WuShigeki TomishimaPatrick StoltShih-Lien Lu
Published in: ISSCC (2017)
Keyphrases
  • prefetching
  • high speed
  • higher level
  • main memory
  • data access
  • web caching
  • hit ratio
  • query processing
  • poisson process
  • memory hierarchy
  • user perceived latency