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Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns.

Nicky LuChun ShiahJuang-Ying ChuehBor-Doou RongWei-Jr HuangHo-Yin ChenCheng-Nan ChangChia-Wei ChangTzung-Shen Chen
Published in: VLSI Circuits (2021)
Keyphrases
  • row column
  • low voltage
  • main memory
  • signal processing
  • multiresolution
  • fast fourier transform