Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns.
Nicky LuChun ShiahJuang-Ying ChuehBor-Doou RongWei-Jr HuangHo-Yin ChenCheng-Nan ChangChia-Wei ChangTzung-Shen ChenPublished in: VLSI Circuits (2021)