Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.
Zhe WangDaniel A. JiménezTao ZhangGabriel H. LohYuan XiePublished in: SBAC-PAD (2016)
Keyphrases
- low latency
- main memory
- high speed
- high bandwidth
- real time
- memory subsystem
- massive scale
- high throughput
- highly efficient
- dynamic random access memory
- data structure
- virtual machine
- stream processing
- continuous query processing
- data access
- query processing
- cost effective
- data collection
- low cost
- motion estimation
- mobile devices
- data sets