An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs.

Yannan Nellie Wu Vivienne Sze Joel S. Emer

Published in: ISPASS (2020)

Keyphrases

compute intensive
computational power
random access
levels of abstraction
data processing
main memory
data sets
parallel implementation
maximum likelihood
least squares
real time
energy consumption
low energy
higher level
high speed
image sequences
memory size