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Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes.
A. Arun Goud
Rangharajan Venkatesan
Anand Raghunathan
Kaushik Roy
Published in:
ACM J. Emerg. Technol. Comput. Syst. (2016)
Keyphrases
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nm technology
shortest path
modal logic
classical logic
power consumption
graph structure
image processing
network structure
directed graph
multi valued
pattern recognition
low cost
signal processing
weighted graph
roc curve
threshold selection