An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS.
Dongsuk JeonMichael B. HenryYejoong KimInhee LeeZhengya ZhangDavid T. BlaauwDennis SylvesterPublished in: IEEE J. Solid State Circuits (2014)
Keyphrases
- feature extraction
- power consumption
- low power
- energy efficiency
- cmos technology
- high speed
- nm technology
- energy efficient
- energy saving
- wireless sensor networks
- power reduction
- low cost
- frame rate
- frequency domain
- metal oxide semiconductor
- silicon on insulator
- image classification
- preprocessing
- image processing
- video frames
- sensor networks
- dimensionality reduction
- feature selection
- single chip
- image sensor
- feature vectors
- face recognition
- extracted features
- feature space
- high density
- feature set
- texture analysis
- low voltage
- circuit design
- wavelet transform
- mac protocol
- delay insensitive
- heavy traffic
- texture features
- principal component analysis
- data flow
- cloud computing
- discriminant analysis
- energy consumption