Michael P. Flynn

ORCID

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 58

Top Venues

IEEE J. Solid State Circuits

ISSCC

CICC

VLSI Technology and Circuits

Publications

Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn
An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer. IEEE J. Solid State Circuits 59 (4) (2024)
Taewook Kang, Seungjong Lee, Seungheun Song, Mohammad Reza Haghighat, Michael P. Flynn
A Multimode 157 μW 4-Channel 80 dBA-SNDR Speech Recognition Frontend With Direction-of-Arrival Correction Adaptive Beamformer. IEEE J. Solid State Circuits 59 (6) (2024)
Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn
An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer. IEEE J. Solid State Circuits 58 (4) (2023)
Seungheun Song, Taewook Kang, Seungjong Lee, Michael P. Flynn
A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C. VLSI Technology and Circuits (2023)
Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn
-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM). VLSI Technology and Circuits (2023)
Rundao Lu, Michael P. Flynn
A Direct Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (10) (2023)
Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn
Order CT SDM with a True TI NS Quantizer. VLSI Technology and Circuits (2022)
Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits (2022)
Xinxin Wang, Reid Pinkham, Mohammed Affan Zidan, Fan-Hsuan Meng, Michael P. Flynn, Zhengya Zhang, Wei D. Lu
TAICHI: A Tiled Architecture for In-Memory Computing and Heterogeneous Integration. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Seungjong Lee, Taewook Kang, John Bell, Mohammad R. Haghighat, Alberto J. Martinez, Michael P. Flynn
An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor. IEEE J. Solid State Circuits 57 (6) (2022)
Taewook Kang, Seungjong Lee, Seungheun Song, Mohammad R. Haghighat, Michael P. Flynn
A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive Beamformer. ISSCC (2022)
Rundao Lu, Christine Weston, Daniel Weyer, Fred N. Buhler, Daniel Lambalot, Michael P. Flynn
Erratum to "A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver". IEEE J. Solid State Circuits 56 (10) (2021)
Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn
A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM. IEEE J. Solid State Circuits 56 (12) (2021)
Boyi Zheng, Lu Jie, Michael P. Flynn
TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping. ESSCIRC (2021)
Rundao Lu, Christine Weston, Daniel Weyer, Fred N. Buhler, Daniel Lambalot, Michael P. Flynn
A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver. IEEE J. Solid State Circuits 56 (5) (2021)
Peter Lawrence Brown, Matthew R. O'Shaughnessy, Christopher Rozell, Justin Romberg, Michael P. Flynn
A 17.8-MS/s Compressed Sensing Radar Accelerator Using a Spiking Neural Network. IEEE J. Solid State Circuits 56 (3) (2021)
Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn
10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer. ISSCC (2021)
Taewook Kang, Seungjong Lee, Mohammad Haghigat, Darren Abramson, Michael P. Flynn
A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction. CICC (2021)
Rundao Lu, Michael P. Flynn
A 300MHz-BW 38mW 37dB/40dB SNDR/DR Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC in 28nm CMOS. VLSI Circuits (2021)
Peter Lawrence Brown, Matthew R. O'Shaughnessy, Christopher J. Rozell, Justin Romberg, Michael P. Flynn
A 17.8MS/s Neural-Network Compressed Sensing Radar Processor in 16nm FinFET CMOS. CICC (2020)
Michael P. Flynn, Jaehun Jeong, Sunmin Jang, Hyungil Chae, Daniel Weyer, Rundao Lu, John Bell
Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited). CICC (2020)
Seungjong Lee, Taewook Kang, John Bell, Mohammad R. Haghighat, Alberto J. Martinez, Michael P. Flynn
An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy. VLSI Circuits (2020)
Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Michael P. Flynn
A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension. IEEE J. Solid State Circuits 55 (12) (2020)
Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Runyu Wang, Michael P. Flynn
-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth. ISSCC (2020)
Daniel Weyer, Mehmet Batuhan Dayanik, Lu Jie, Ahmed Albalawi, Abdulhamed Alothaimen, Mohammed Aseeri, Michael P. Flynn
Design Considerations for Integrated Radar Chirp Synthesizers. IEEE Access 7 (2019)
John Bell, Michael P. Flynn
A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS. ESSCIRC (2019)
Lu Jie, Boyi Zheng, Michael P. Flynn
A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC. IEEE J. Solid State Circuits 54 (12) (2019)
Lu Jie, Boyi Zheng, Michael P. Flynn
-Order Noise-Shaping SAR ADC. ISSCC (2019)
Sunmin Jang, Rundao Lu, Jaehun Jeong, Michael P. Flynn
A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer. IEEE J. Solid State Circuits 54 (5) (2019)
Mehmet Batuhan Dayanik, Michael P. Flynn
Digital Fractional-N PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System. IEEE J. Solid State Circuits 53 (6) (2018)
Daniel Weyer, Mehmet Batuhan Dayanik, Sunmin Jang, Michael P. Flynn
40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter. ISSCC (2018)
Sunmin Jang, Jaehun Jeong, Rundao Lu, Michael P. Flynn
A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS. IEEE J. Solid State Circuits 53 (5) (2018)
Shiming Song, Kyojin David Choo, Thomas Chen, Sunmin Jang, Michael P. Flynn, Zhengya Zhang
A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2018)
Adam E. Mendrela, Sung-Yun Park, Mihály Vöröslakos, Michael P. Flynn, Euisik Yoon
A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping. VLSI Circuits (2018)
Nicholas Collins, Andres Tamez, Lu Jie, Jorge Pernillo, Michael P. Flynn
A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
John Bell, Phil Knag, Shuanghong Sun, Yong Lim, Thomas Chen, Jeffrey Fredenburg, Chia-Hsiang Chen, Chunyang Zhai, Aaron Z. Rocca, Nicholas Collins, Andres Tamez, Jorge Pernillo, Justin M. Correll, Alan B. Tanner, Zhengya Zhang, Michael P. Flynn
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging. IEEE J. Solid State Circuits 52 (5) (2017)
Yashar Rajavi, Mohammad Mahdi Ghahramani, Alireza Khalili, Amirpouya Kavousian, Beomsup Kim, Michael P. Flynn
A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS. IEEE J. Solid State Circuits 52 (10) (2017)
Adam E. Mendrela, Jihyun Cho, Jeffrey A. Fredenburg, Vivek Nagaraj, Theoden I. Netoff, Michael P. Flynn, Euisik Yoon
A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression. IEEE J. Solid State Circuits 51 (4) (2016)
Michael P. Flynn, Pietro Andreani, SeongHwan Cho
New Associate Editors. IEEE J. Solid State Circuits 51 (5) (2016)
Michael P. Flynn
Message From the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits 51 (8) (2016)
Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey A. Fredenburg, Michael P. Flynn
A 16-channel noise-shaping machine learning analog-digital interface. VLSI Circuits (2016)
Michael P. Flynn
Introducing Short Regular Papers. IEEE J. Solid State Circuits 51 (3) (2016)
Kyojin David Choo, John Bell, Michael P. Flynn
27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC. ISSCC (2016)
Michael P. Flynn
New Associate Editor. IEEE J. Solid State Circuits 51 (3) (2016)
Hyungil Chae, Michael P. Flynn
A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability. IEEE J. Solid State Circuits 51 (3) (2016)
Jaehun Jeong, Nicholas Collins, Michael P. Flynn
A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators. IEEE J. Solid State Circuits 51 (5) (2016)
Michael P. Flynn
Introducing BrowZine, a Tablet and Phone-Based Reader for the JSSC. IEEE J. Solid State Circuits 51 (3) (2016)
Jeffrey Fredenburg, Michael P. Flynn
ADC trends and impact on SAR ADC architecture and analysis. CICC (2015)
Mehmet Batuhan Dayanik, Nicholas Collins, Michael P. Flynn
order noise shaping time-to-digital converter with 176fs resolution. ESSCIRC (2015)
Adam E. Mendrela, Jihyun Cho, Jeffrey A. Fredenburg, Cynthia A. Chestek, Michael P. Flynn, Euisik Yoon
Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression. VLSIC (2015)
Michael P. Flynn
New Associate Editor. IEEE J. Solid State Circuits 50 (4) (2015)
Michael P. Flynn
New Associate Editor. IEEE J. Solid State Circuits 50 (7) (2015)
Michael P. Flynn
New Associate Editor. IEEE J. Solid State Circuits 50 (6) (2015)
Yong Lim, Michael P. Flynn
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC. IEEE J. Solid State Circuits 50 (12) (2015)
Yong Lim, Michael P. Flynn
26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC. ISSCC (2015)
Michael P. Flynn
New Associate Editors. IEEE J. Solid State Circuits 50 (1) (2015)
Michael P. Flynn
New Associate Editor. IEEE J. Solid State Circuits 50 (11) (2015)
Yong Lim, Michael P. Flynn
A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers. IEEE J. Solid State Circuits 50 (10) (2015)
Michael P. Flynn
New Associate Editors. IEEE J. Solid State Circuits 49 (7) (2014)
Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF. IEEE J. Solid State Circuits 49 (2) (2014)
Michael P. Flynn
New Associate Editor. IEEE J. Solid State Circuits 49 (3) (2014)
Michael P. Flynn
New Associate Editor. IEEE J. Solid State Circuits 49 (1) (2014)
Yong Lim, Michael P. Flynn
11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers. ISSCC (2014)
Chunyang Zhai, Jeffrey Fredenburg, John Bell, Michael P. Flynn
An N-path filter enhanced low phase noise ring VCO. VLSIC (2014)
Michael P. Flynn
New Associate Editor [Ken Suyama]. IEEE J. Solid State Circuits 49 (10) (2014)
Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management. IEEE J. Solid State Circuits 49 (10) (2014)
Michael P. Flynn
Message From the Incoming Editor-in-Chief. IEEE J. Solid State Circuits 48 (8) (2013)
Jorge Pernillo, Michael P. Flynn
A 9b 2GS/s 45mW 2X-interleaved ADC. ESSCIRC (2013)
Michael P. Flynn, John Khoury
EP2: You're hired! The top 25 interview questions for circuit designers. ISSCC (2013)
Michael P. Flynn
New Associate Editor. IEEE J. Solid State Circuits 48 (9) (2013)
Jeffrey Fredenburg, Michael P. Flynn
A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC. ISSCC (2012)
Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn
A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders. VLSIC (2012)
David T. Lin, Li Li, Shahin Farahani, Michael P. Flynn
A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2012)
Hyo-Gyuem Rhew, Michael P. Flynn, JunYoung Park
A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination. ESSCIRC (2012)
Jeffrey Fredenburg, Michael P. Flynn
Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2012)
Jeffrey Fredenburg, Michael P. Flynn
A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC. IEEE J. Solid State Circuits 47 (12) (2012)
Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn
A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. ISSCC (2012)
Praveen K. Yenduri, Aaron Z. Rocca, Aswin S. Rao, Shahrzad Naraghi, Michael P. Flynn, Anna C. Gilbert
A Low-Power Compressive Sampling Time-Based Analog-to-Digital Converter. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (3) (2012)
Praveen K. Yenduri, Anna C. Gilbert, Michael P. Flynn, Shahrzad Naraghi
Rand PPM: A lowpower compressive sampling analog to digital converter. ICASSP (2011)
Chun C. Lee, Michael P. Flynn
A 14 b 23 MS/s 48 mW Resetting Sigma Delta ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Chun C. Lee, Michael P. Flynn
A SAR-Assisted Two-Stage Pipeline ADC. IEEE J. Solid State Circuits 46 (4) (2011)
Jorge Pernillo, Michael P. Flynn
A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS. IEEE Trans. Circuits Syst. II Express Briefs (12) (2011)
Andres Tamez, Jeffrey A. Fredenburg, Michael P. Flynn
An integrated 120 volt AC mains voltage interface in standard 130 nm CMOS. ESSCIRC (2010)
Jongwoo Lee, Hyo-Gyuem Rhew, Daryl R. Kipke, Michael P. Flynn
A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC. IEEE J. Solid State Circuits 45 (9) (2010)
David T. Lin, Li Li, Shahin Farahani, Michael P. Flynn
A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC. CICC (2010)
Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn
Pulse Position Modulation ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits 45 (9) (2010)
Mark A. Ferriss, David T. Lin, Michael P. Flynn
A fractional-N PLL modulator with flexible direct digital phase modulation. CICC (2009)
JunYoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn
A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2009)
Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn
PPM ADC in 90nm digital CMOS. ISSCC (2009)
Jongwoo Lee, Joshua Jaeyoung Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. IEEE J. Solid State Circuits 44 (10) (2009)
JunYoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn
A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines. CICC (2008)
Mark A. Ferriss, Michael P. Flynn
A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme. IEEE J. Solid State Circuits 43 (11) (2008)
Joshua Jaeyoung Kang, David T. Lin, Li Li, Michael P. Flynn
A reconfigurable FIR filter embedded in a 9b successive approximation ADC. CICC (2008)
Ivan Bogue, Michael P. Flynn
A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS. CICC (2007)
Jia-Yi Chen, Michael P. Flynn, John P. Hayes
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS. IEEE J. Solid State Circuits 42 (9) (2007)
Sunghyun Park, Yorgos Palaskas, Michael P. Flynn
A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS. IEEE J. Solid State Circuits 42 (9) (2007)
Mark A. Ferriss, Michael P. Flynn
A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme. ISSCC (2007)
Fatih Kocer, Michael P. Flynn
A new transponder architecture with on-chip ADC for long-range telemetry applications. IEEE J. Solid State Circuits 41 (5) (2006)
Sunghyun Park, Yorgos Palaskas, Michael P. Flynn
A 4GS/s 4b Flash ADC in 0.18µm CMOS. ISSCC (2006)
Jia-Yi Chen, Michael P. Flynn, John P. Hayes
A Fully Integrated Auto-Calibrated SuperRegenerative Receiver. ISSCC (2006)

Michael P. Flynn.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Michael P. Flynn