A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS.

Ivan Bogue Michael P. Flynn

Published in: CICC (2007)

Keyphrases

analog to digital converter
circuit design
cmos image sensor
low power
high speed
wide dynamic range
single chip
real time
low cost
image sensor
analog vlsi
power consumption
neural network
imaging systems
protein folding
mixed signal
multi view
vlsi circuits
sigma delta
digital images
image registration