Beomsup Kim

Publication Activity (10 Years)

Years Active: 1993-2017
Publications (10 Years): 1

Top Topics

Feature Selection

Parallel Processing

Top Venues

IEEE J. Solid State Circuits

Publications

Yashar Rajavi, Mohammad Mahdi Ghahramani, Alireza Khalili, Amirpouya Kavousian, Beomsup Kim, Michael P. Flynn
A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS. IEEE J. Solid State Circuits 52 (10) (2017)
Shen Wang, Vipul Chawla, Dong Sam Ha, Beomsup Kim
Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-Two. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2012)
Shen Wang, Dong Sam Ha, Beomsup Kim, Vipul Chawla
A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation. CICC (2011)
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators. IEEE J. Solid State Circuits 40 (4) (2005)
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". IEEE J. Solid State Circuits 40 (11) (2005)
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
Hybrid ΣΔ modulators with adaptive calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2005)
Seok Kang, Beomsup Kim
A DLL-Based Frequency Synthesizer with Selective Reuse of a Delay Cell Scheme for 2.4 GHz ISM Band. IEICE Trans. Electron. (1) (2005)
Jaesang Lim, Jaejoon Kim, Beomsup Kim
Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Jaesang Lim, Yongchul Song, Jeong Pyo Kim, Beomsup Kim
An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, C. S. G. Conroy, Beomsup Kim
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer. IEEE J. Solid State Circuits 40 (2) (2005)
Yongchul Song, Beomsup Kim
A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR. IEEE J. Solid State Circuits 39 (11) (2004)
Yongchul Song, Beomsup Kim
A 14-b direct digital frequency synthesizer with sigma-delta noise shaping. IEEE J. Solid State Circuits 39 (5) (2004)
Yongchul Song, Beomsup Kim
Quadrature direct digital frequency synthesizers using interpolation-based angle rotation. IEEE Trans. Very Large Scale Integr. Syst. 12 (7) (2004)
Yongchul Song, Beomsup Kim
Low-jitter digital timing recovery techniques for CAP-based VDSL applications. IEEE J. Solid State Circuits 38 (10) (2003)
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
A hybrid delta-sigma modulator with adaptive calibration. ISCAS (1) (2003)
Sangjin Byun, Chan-Hong Park, Yongchul Song, Sung-Ho Wang, Cormac S. G. Conroy, Beomsup Kim
A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator. IEEE J. Solid State Circuits 38 (10) (2003)
Yongchul Song, Beomsup Kim
A 330-MHz 15-b quadrature digital synthesizer/mixer in 0.25-μm CMOS. ESSCIRC (2003)
Hyung Ki Ahn, In-Cheol Park, Beomsup Kim
A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. ISCAS (1) (2003)
Yongchul Song, Kyehyung Lee, Beomsup Kim
Digital timing synchronization with jitter reduction technique for cap-based VDSL system. ICASSP (2001)
Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam, Young Gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. IEEE J. Solid State Circuits 36 (4) (2001)
Chan-Hong Park, Ook Kim, Beomsup Kim
A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching. IEEE J. Solid State Circuits 36 (5) (2001)
Joonsuk Lee, Beomsup Kim
A low-noise fast-lock phase-locked loop with adaptive bandwidth control. IEEE J. Solid State Circuits 35 (8) (2000)
Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim, Beomsup Kim
A low-noise phase-locked loop design by loop bandwidth optimization. IEEE J. Solid State Circuits 35 (6) (2000)
Jae Joon Kim, Sang-Bo Lee, Tae-Sung Jung, Chang-Hyun Kim, Soo-In Cho, Beomsup Kim
A low-jitter mixed-mode DLL for high-speed DRAM applications. IEEE J. Solid State Circuits 35 (10) (2000)
Beomsup Kim, Joonsuk Lee, Seung Hee Choi, Jun Mo Koo, Byung Jun Min
Non-Data-Aided Timing Recovery Algorithm for \pi/4-OPSK Modulated Signals. ICC (1) (2000)
Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. ASP-DAC (1999)
Chan-Hong Park, Beomsup Kim
A low-noise, 900-MHz VCO in 0.6-μm CMOS. IEEE J. Solid State Circuits 34 (5) (1999)
Chang-Hyun Kim, Jung-Hwa Lee, J. B. Lee, Beomsup Kim, C. S. Park, Sang-Bo Lee, S. Y. Lee, C. W. Park, J. G. Roh, Hyoung Sik Nam, D. Y. Kim, D. Y. Lee, Tae-Sung Jung, Hongil Yoon, Soo-In Cho
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. IEEE J. Solid State Circuits 33 (11) (1998)
Tae Hun Kim, Beomsup Kim
Dual-loop Digital PLL Design for Adaptive Clock Recovery. ASP-DAC (1998)
Seog-Jun Lee, Beomsup Kim, Kwyro Lee
A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application. IEEE J. Solid State Circuits 32 (5) (1997)
Kyoo Hyun Lim, Seung Hee Choi, Beomsup Kim
Optimal loop bandwidth design for low noise PLL applications. ASP-DAC (1997)
Byungjin Chun, Seung Hee Choi, Beomsup Kim
A Digital Phase-Locked Loop with Variable Loop Gains Derived from RLS Method. ICC (1) (1997)
Seog-Jun Lee, Beomsup Kim, Kwyro Lee
A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme. IEEE J. Solid State Circuits 32 (2) (1997)
Byungjin Chun, Yong Hoon Lee, Beomsup Kim
Design of variable loop gains of dual-loop DPLL. IEEE Trans. Commun. 45 (12) (1997)
Jeongsik Yang, Chanhong Park, Beomsup Kim
A digital audio signal processor for cellular phone application. ASP-DAC (1995)
Byungjin Chun, Beomsup Kim, Yong Hong Lee
Adaptive Carrier Recovery Using Multi-Order DPLL for Mobile Communication Applications. ISCAS (1995)
Beomsup Kim, Todd C. Weigandt, Paul R. Gray
PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design. ISCAS (1994)
Todd C. Weigandt, Beomsup Kim, Paul R. Gray
Analysis of Timing Jitter in CMOS Ring Oscillators. ISCAS (1994)
Beomsup Kim
Optical MMSE gear-shifting algorithm for the fast synchronization of DPLL. ISCAS (1993)