Jae Hoon Shim

Publication Activity (10 Years)

Years Active: 2001-2023
Publications (10 Years): 9

Top Topics

Lossless Image Compression

Network Intrusion

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Dong-Jick Min, Jun-Gi Lee, Kunhee Cho, Jae Hoon Shim
An Output-Capacitor-Free Adaptive-Frequency Digital LDO with a 420-mA Load Current and a Fast Settling Time. ISCAS (2023)
Jaejin Kim, Gunmo Koo, Seongmin Lee, Jae Hoon Shim, Kunhee Cho
An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Geonsu Lee, Hochang Rhee, Jae Hoon Shim, Hyung Il Koo, Nam Ik Cho
Network Intrusion Detection with Improved Feature Representation. APSIPA ASC (2021)
Dong-Jick Min, Jae Hoon Shim
A Zero-Crossing-Based Integrator with Bidirectional Two-Phase Charging and Selective-Reset Operations for ΔΣ ADCs. ISCAS (2021)
Jae Hoon Shim, Hochang Rhee, Yeong Il Jang, Geonsu Lee, Seyun Kim, Nam Ik Cho
Lossless Image Compression Based on Image Decomposition and Progressive Prediction Using Convolutional Neural Networks. APSIPA ASC (2021)
Seung-Ho Ok, Jae Hoon Shim, Byungin Moon
Modified adaptive support weight and disparity search range estimation schemes for stereo matching processors. J. Supercomput. 74 (12) (2018)
Dong-Jick Min, Sun Youl Choi, Jae Hoon Shim
A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing Detector. ICECS (2018)
Changho Yoon, Jae Hoon Shim, Byungin Moon, Joonho Kong
3D die-stacked DRAM thermal management via task allocation and core pipeline control. IEICE Electron. Express 15 (3) (2018)
Seung-Ho Ok, Yong-Hwan Lee, Jae Hoon Shim, Sung Kyu Lim, Byungin Moon
The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors. Sensors 17 (2) (2017)
Sangjin Byun, Jae Hoon Shim
Charge Pump circuit with wide range digital leakage current mismatch compensator. IEICE Electron. Express 7 (23) (2010)
Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector. IEEE J. Solid State Circuits 41 (11) (2006)
Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu
A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector. ISSCC (2006)
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators. IEEE J. Solid State Circuits 40 (4) (2005)
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". IEEE J. Solid State Circuits 40 (11) (2005)
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
Hybrid ΣΔ modulators with adaptive calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2005)
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
A hybrid delta-sigma modulator with adaptive calibration. ISCAS (1) (2003)
Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam, Young Gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. IEEE J. Solid State Circuits 36 (4) (2001)