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A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators.
Jae Hoon Shim
In-Cheol Park
Beomsup Kim
Published in:
IEEE J. Solid State Circuits (2005)
Keyphrases
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spl times
mixed mode
case study
low cost
high speed