Jorge Guilherme

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 12

Top Topics

Higher Dimensional

Architectural Design

Top Venues

Publications

Fábio Passos, Rafael Vieira, António Canelas, Ricardo Póvoa, Nuno Lourenço, Nuno Horta, Jorge Guilherme
A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications. ISCAS (2022)
Nuno Lourenço, Fábio Passos, Rafael Vieira, Ricardo Martins, Nuno Horta, Jorge Guilherme, Ricardo Póvoa
Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient. SMACD (2022)
Rafáel Vieira, Fábio Passos, Ricardo Povoa, Ricardo Martins, Nuno Horta, Jorge Guilherme, Nuno Lourenço
Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling. SMACD (2022)
António Canelas, Ricardo Póvoa, Ricardo Martins, Nuno Lourenço, Jorge Guilherme, João Paulo Carvalho, Nuno Horta
-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
António Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço, Jorge Guilherme, Nuno Horta
A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications. SMACD (2018)
Jigme Zangpo, Ricardo Povoa, Jorge Guilherme, Nuno Horta
An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations. ICECS (2018)
Jonathan Calvillo, Ricardo Póvoa, Jorge Guilherme, Nuno Horta
Second-order compensation BGR with low TC and high performance for space applications. Integr. 63 (2018)
Rodrigo Granja, Mauro Santos, Jorge Guilherme, Nuno Horta
11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology. PRIME (2018)
Jonathan Calvillo, Jorge Guilherme, Nuno Horta
Design of a BGR Suitable for the Space Industry with Performance of 1.25 V with 0.758 ppm/°C TC from - 55° to 125°C. NGCAS (2017)
Jose Cachaco, Nuno Machado, Nuno Lourenço, Jorge Guilherme, Nuno Horta
Automatic technology migration of analog IC designs using generic cell libraries. DATE (2017)
Carlos Silva, Jorge Guilherme, Nuno Horta
SCALES: A high speed simulator tool for pipeline A/D converters. SMACD (2016)
Mauro Santos, Nuno Horta, Jorge Guilherme
Logarithmic AD Converter With Selectable Transfer Characteristic. IEEE Trans. Circuits Syst. II Express Briefs (3) (2016)
David Guilherme, João Pereira, Nuno Horta, Jorge Guilherme
Thermal-aware floorplanning and layout generation of MOSFET power stages. ISCAS (2015)
Bruno Silva, Nuno Horta, Jorge Guilherme
A rad-hard DC-DC converter controller. ICECS (2014)
Mauro Santos, Nuno Horta, Jorge Guilherme
Logarithmic AD conversion using latched comparators and a time-to-digital converter. ICECS (2014)
David Guilherme, Nuno Horta, Jorge Guilherme
Automatic layout generation of power MOSFET transistors in bulk CMOS. ICECS (2014)
Mauro Santos, Nuno Horta, Jorge Guilherme
A survey on nonlinear analog-to-digital converters. Integr. 47 (1) (2014)
Frederico Cadete, David Guilherme, Jorge Guilherme, Nuno Horta
Overcurrent detection circuit for integrated class-D amplifiers. ECCTD (2011)
Pedro Sousa, Carla Duarte, Manuel F. M. Barros, Jorge Guilherme, Nuno Horta
Optimal OpAmp sizing based on a fuzzy-genetic kernel. GECCO (Companion) (2011)
Manuel F. M. Barros, Jorge Guilherme, Nuno Horta
Analog circuits optimization based on evolutionary computation techniques. Integr. 43 (1) (2010)
Alexandre Ribeiro, António Sirgado, João Aperta, Ana C. Lopes, Jorge Guilherme, Pedro D. F. Correia, Gabriel Pires, Urbano Nunes
A Low-cost EEG Stand-alone Device for Brain Computer Interface. BIODEVICES (2009)
Artur Silva, Jorge Guilherme, Nuno Horta
Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals. Integr. 42 (1) (2009)
Pedro Sousa, Carla Duarte, Manuel F. M. Barros, Jorge Guilherme, Nuno Horta
Enhancing analog IC design optimization kernels with simple fuzzy models. ECCTD (2009)
Jongwoo Lee, Joshua Jaeyoung Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. IEEE J. Solid State Circuits 44 (10) (2009)
Artur Silva, Nuno Horta, Jorge Guilherme
A reconfigurable A/D converter for 4G wireless systems. ISCAS (2008)
Mauro Santos, Carlos Pires, Jorge Guilherme, Nuno Horta
Overview of radiation effects and design constraints off fully custom SMPS. APCCAS (2008)
Manuel F. M. Barros, Jorge Guilherme, Nuno Horta
GA-SVM feasibility model and optimization kernel applied to analog IC design automation. ACM Great Lakes Symposium on VLSI (2007)
Manuel F. M. Barros, Jorge Guilherme, Nuno Horta
An evolutionary optimization kernel using a dynamic GA-SVM model applied to analog IC design. ECCTD (2007)
Artur Silva, Nuno Horta, Jorge Guilherme
Design of a multimode reconfigurable sigma-delta converter for 4G wireless receivers. ECCTD (2007)
Manuel F. M. Barros, Jorge Guilherme, Nuno Horta
GA-SVM Optimization Kernel applied to Analog IC Design Automation. ICECS (2006)
Jorge Guilherme, João C. Vital, José E. Franca
A CMOS logarithmic pipeline A/D converter with a dynamic range of 80 dB. ICECS (2002)
Jorge Guilherme, João C. Vital, José E. Franca
A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction. ICECS (2001)
Jorge Guilherme, Pedro M. Figueiredo, Pedro Azevedo, Goncalo Minderico, Antonio Leal, João C. Vital, José E. Franca
A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications. ISCAS (1) (2001)
Jorge Guilherme, Pedro M. Figueiredo, P. Azevedo, G. Minderico, A. Leal, João C. Vital, José E. Franca
Design considerations for high resolution pipeline ADCs in digital CMOS technology. ICECS (2001)
Jorge Guilherme, Nuno C. G. Horta, José E. Franca
Symbolic synthesis of non-linear data converters. ICECS (1998)
Jorge Guilherme, José E. Franca
New CMOS Logarithmic A/D Converters Employing Pipeline and Algorithmic Architectures. ISCAS (1995)
Jorge Guilherme, José E. Franca
Digitally-Controlled Analogue Signal Processing and Conversion Techniques Employing a Logarithmic Building Block. ISCAS (1994)