António Canelas

Publication Activity (10 Years)

Years Active: 2012-2022
Publications (10 Years): 27

Top Topics

Evolutionary Optimization

Artificial Neural Networks

Monte Carlo Simulation

Pattern Discovery

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Fábio Passos, Rafael Vieira, António Canelas, Ricardo Póvoa, Nuno Lourenço, Nuno Horta, Jorge Guilherme
A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications. ISCAS (2022)
António Canelas, Fábio Passos, Nuno Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. IEEE Access 9 (2021)
Ricardo Póvoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes
A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications. IEEE Trans. Circuits Syst. II Express Briefs (2) (2020)
António Canelas, Ricardo Póvoa, Ricardo Martins, Nuno Lourenço, Jorge Guilherme, João Paulo Carvalho, Nuno Horta
-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
Ricardo Póvoa, Richa Arya, António Canelas, Fábio Passos, Ricardo Martins, Nuno Lourenço, Nuno Horta
Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications. Microelectron. J. 95 (2020)
Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes
A new family of CMOS inverter-based OTAs for biomedical and healthcare applications. Integr. 71 (2020)
Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Póvoa, Nuno Horta, Emmanuel Moutaye
Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization. SMACD (2019)
Nuno Lourenço, Engin Afacan, Ricardo Martins, Fábio Passos, António Canelas, Ricardo Póvoa, Nuno Horta, Günhan Dündar
Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing. SMACD (2019)
Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins
Artificial Neural Networks as an Alternative for Automatic Analog IC Placement. SMACD (2019)
Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes
A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers. SMACD (2019)
António Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço, Jorge Guilherme, Nuno Horta
A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications. SMACD (2018)
João Baúto, António Canelas, Rui Ferreira Neves, Nuno Horta
Parallel SAX/GA for financial pattern matching using NVIDIA's GPU. Expert Syst. Appl. 105 (2018)
Nuno Lourenço, Joao Rosa, Ricardo Martins, Helena Aidos, António Canelas, Ricardo Povoa, Nuno Horta
On the Exploration of Promising Analog IC Designs via Artificial Neural Networks. SMACD (2018)
Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. SMACD (2018)
Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. Integr. 63 (2018)
Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Cavaco Gomes Horta, João Goes
Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement. IEEE Trans. Circuits Syst. II Express Briefs (3) (2018)
Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes
Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta
Systematic design of a voltage controlled oscillator using a layout-aware approach. SMACD (2017)
Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. SMACD (2017)
António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing. DATE (2017)
Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. SMACD (2017)
Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
Stochastic-based placement template generator for analog IC layout-aware synthesis. Integr. 58 (2017)
António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations. SMACD (2016)
Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. Integr. 55 (2016)
Ricardo Martins, António Canelas, Nuno Lourenço, Nuno Horta
On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies. SMACD (2016)
Mrinalinee Pandey, António Canelas, Ricardo Póvoa, Jorge Alves Torres, João Costa Freire, Nuno Lourenço, Nuno Horta
Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer. Integr. 55 (2016)
Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
Extraction and application of wiring symmetry rules to route analog multiport terminals. ISCAS (2015)
Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta
Floorplan-aware analog IC sizing and optimization based on topological constraints. Integr. 48 (2015)
Ricardo Povoa, Ricardo Lourenco, Nuno Lourenço, António Canelas, Ricardo Martins, Nuno Horta
LC-VCO automatic synthesis using multi-objective evolutionary techniques. ISCAS (2014)
Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
Electromigration-aware analog Router with multilayer multiport terminal structures. Integr. 47 (4) (2014)
Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures. DATE (2014)
Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
Multi-port multi-terminal analog router based on an evolutionary optimization kernel. IEEE Congress on Evolutionary Computation (2013)
António Canelas, Rui Ferreira Neves, Nuno Horta
Multi-dimensional pattern discovery in financial time series using sax-ga with extended robustness. GECCO (Companion) (2013)
António Canelas, Rui Ferreira Neves, Nuno Horta
A SAX-GA approach to evolve investment strategies on financial markets based on pattern discovery techniques. Expert Syst. Appl. 40 (5) (2013)
António Canelas, Rui Ferreira Neves, Nuno Horta
A new SAX-GA methodology applied to investment strategies optimization. GECCO (2012)