Javier J. Sieiro

Publication Activity (10 Years)

Years Active: 2010-2020
Publications (10 Years): 8

Top Topics

Optimization Algorithm

Radio Frequency

Disturbance Rejection

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Fábio Passos, Elisenda Roca, Ricardo Martins, Nuno Lourenço, Saiyd Ahyoune, Javier J. Sieiro, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology. IEEE Access 8 (2020)
Fábio Passos, Elisenda Roca, Javier J. Sieiro, Rafaella Fiorelli, Rafael Castro-López, José María López-Villegas, Francisco V. Fernández
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (3) (2020)
Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator. Integr. 63 (2018)
Arnau Salas Barenys, Neus Vidal, Javier J. Sieiro, José María López-Villegas, B. Medina-Rodriguez, F. M. Ramos
Fabrication of Full-3D Printed Electronics RF Passive Components and Circuits. PRIME (2018)
Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Javier J. Sieiro, José María López-Villegas, Neus Vidal
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (1) (2017)
Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández
Extending the frequency range of quasi-static electromagnetic solvers. SMACD (2017)
Elisenda Roca, Javier J. Sieiro
Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques. Integr. 52 (2016)
Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier J. Sieiro, Neus Vidal, José María López-Villegas
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
David Gascon, Andreu Sanuy, Javier J. Sieiro
Compact class-AB follower for wideband closed loop line drivers. ICECS (2012)
Ignacio Gil, Ignasi Cairó, Javier J. Sieiro, José María López-Villegas
Low-power current-reused RF front-end based on optimized transformers topology. Integr. 43 (2) (2010)
Ignacio Gil, Raúl Fernández, Javier J. Sieiro, José María López-Villegas
Optimized passive devices for low-power LNA design. ICECS (2010)