Optimized passive devices for low-power LNA design.

Ignacio Gil Raúl Fernández Javier J. Sieiro José María López-Villegas

Published in: ICECS (2010)

Keyphrases

low power
low power consumption
power consumption
single chip
high speed
low cost
vlsi architecture
logic circuits
digital signal processing
high power
mixed signal
cmos technology
gate array
design process
general purpose
real time
ultra low power
power reduction
embedded systems
motion estimation