Ricardo Povoa

Publication Activity (10 Years)

Years Active: 2013-2022
Publications (10 Years): 18

Top Topics

Monte Carlo Simulation

Architectural Design

Optimization Method

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Rafáel Vieira, Fábio Passos, Ricardo Povoa, Ricardo Martins, Nuno Horta, Jorge Guilherme, Nuno Lourenço
Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling. SMACD (2022)
Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
António Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço, Jorge Guilherme, Nuno Horta
A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications. SMACD (2018)
Jigme Zangpo, Ricardo Povoa, Jorge Guilherme, Nuno Horta
An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations. ICECS (2018)
Nuno Lourenço, Joao Rosa, Ricardo Martins, Helena Aidos, António Canelas, Ricardo Povoa, Nuno Horta
On the Exploration of Promising Analog IC Designs via Artificial Neural Networks. SMACD (2018)
Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. SMACD (2018)
Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. Integr. 63 (2018)
Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Cavaco Gomes Horta, João Goes
Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement. IEEE Trans. Circuits Syst. II Express Briefs (3) (2018)
Tiago Pessoa, Nuno Lourenço, Ricardo Martins, Ricardo Povoa, Nuno Horta
Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel. DATE (2018)
Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes
Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta
Systematic design of a voltage controlled oscillator using a layout-aware approach. SMACD (2017)
Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. SMACD (2017)
António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing. DATE (2017)
Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. SMACD (2017)
Ricardo Povoa, Ivan Bastos, Nuno Lourenço, Nuno Horta
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques. Integr. 52 (2016)
António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations. SMACD (2016)
Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. Integr. 55 (2016)
Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
Current-flow and current-density-aware multi-objective optimization of analog IC placement. Integr. 55 (2016)
Ricardo Povoa, Nuno Lourenço, Nuno Horta, João Goes
A voltage-combiners-biased amplifier with enhanced gain and speed using current starving. ISCAS (2015)
Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta
Floorplan-aware analog IC sizing and optimization based on topological constraints. Integr. 48 (2015)
Ricardo Povoa, Ricardo Lourenco, Nuno Lourenço, António Canelas, Ricardo Martins, Nuno Horta
LC-VCO automatic synthesis using multi-objective evolutionary techniques. ISCAS (2014)
Ricardo Povoa, Nuno Lourenço, Nuno Horta, Rui Santos-Tavares, João Goes
A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner. ICECS (2014)
Frederico Rocha, Nuno Lourenço, Ricardo Povoa, Ricardo Martins, Nuno Horta
A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis. IEEE Congress on Evolutionary Computation (2013)
Ricardo Povoa, Nuno Lourenço, Nuno Horta, Rui Santos-Tavares, João Goes
Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners. VLSI-SoC (2013)