Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs.
António CanelasFábio PassosNuno LourençoRicardo MartinsElisenda RocaRafael Castro-LópezNuno HortaFrancisco V. FernándezPublished in: IEEE Access (2021)
Keyphrases
- analog circuits
- higher level
- semiconductor devices
- logic synthesis
- hierarchical structure
- hierarchical structures
- levels of abstraction
- information retrieval
- real time
- high speed
- data acquisition
- database
- coarse to fine
- design methodology
- expert systems
- hierarchical classification
- decision trees
- artificial intelligence
- analog vlsi