New CMOS Logarithmic A/D Converters Employing Pipeline and Algorithmic Architectures.

Jorge Guilherme José E. Franca

Published in: ISCAS (1995)

Keyphrases

high speed
circuit design
power consumption
analog vlsi
low cost
low power
neural architectures
worst case
power supply
delay insensitive
neural network
steady state
image processing
artificial intelligence
data mining
single chip
processing pipeline
real time