Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble.
Koichi MitsunariJaehoon YuTakao OnoyeMasanori HashimotoPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2018)
Keyphrases
- hardware architecture
- high speed
- object detection
- decision trees
- ensemble methods
- random forest
- decision tree classifiers
- random forests
- base classifiers
- hardware implementation
- training set
- hardware architectures
- training data
- low power
- multi class
- ensemble classifier
- computer vision
- ensemble learning
- face detection
- logistic regression
- naive bayes
- machine learning algorithms
- machine learning
- field programmable gate array
- associative memory
- prediction accuracy
- pruning algorithm
- processing elements
- real time
- neural network
- classification models
- object recognition
- efficient implementation
- learning algorithm
- block matching motion estimation
- signal processing
- feature vectors
- image processing
- information systems