Minimizing detection-to-boosting latency toward low-power error-resilient circuits.
Chih-Cheng HsuMasanori HashimotoMark Po-Hung LinPublished in: Integr. (2017)
Keyphrases
- low power
- high speed
- error resilient
- logic circuits
- power consumption
- low cost
- cmos technology
- power dissipation
- mixed signal
- power reduction
- error propagation
- image transmission
- coding scheme
- low density parity check
- error resilience
- error detection
- video streaming
- vlsi architecture
- video transmission
- bitstream
- compressed video
- jpeg images
- channel coding
- error concealment
- video quality
- image compression