Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits.
Chih-Cheng HsuMark Po-Hung LinMasanori HashimotoPublished in: SLIP (2016)
Keyphrases
- low power
- high speed
- power reduction
- power consumption
- logic circuits
- low cost
- cmos technology
- vlsi circuits
- mixed signal
- power dissipation
- delay insensitive
- single chip
- clustering algorithm
- high power
- digital signal processing
- wireless transmission
- vlsi architecture
- image sensor
- information theoretic
- real time
- gate array
- power saving
- response time