Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V -.
Liao WangSoichi HirokawaRyo HaradaMasanori HashimotoPublished in: NEWCAS (2017)
Keyphrases
- error rate
- high speed
- analog vlsi
- cmos technology
- equal error rate
- test set
- circuit design
- low power
- power consumption
- silicon on insulator
- power dissipation
- misclassification rate
- random access memory
- lower error rates
- low voltage
- logic circuits
- word error rate
- rejection rate
- cost sensitive classification
- evolvable hardware
- chip design