Soft error immune latch design for 20 nm bulk CMOS.

Taiki Uemura Takashi Kato Hideya Matsuyama Masanori Hashimoto

Published in: IRPS (2015)

Keyphrases

power consumption
low power
cmos technology
design process
case study
user interface
low cost
design methodology
learning algorithm
high speed
anomaly detection
building blocks
error rate
single chip