Spandana Rachamalla

Publication Activity (10 Years)

Years Active: 2015-2019
Publications (10 Years): 3

Top Topics

Formal Verification

High Efficiency

Top Venues

IET Comput. Digit. Tech.

Publications

Arun Joseph, Spandana Rachamalla, Shashidhar Reddy, Nagu R. Dhanwada
Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis. VLSI Design (2019)
Spandana Rachamalla, Shashidhar Reddy, Arun Joseph
Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors. IET Comput. Digit. Tech. 13 (6) (2019)
Arun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla
FVCAG: A framework for formal verification driven power modeling and verification. ISLPED (2016)
Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey
Virtual logic netlist: Enabling efficient RTL analysis. ISQED (2015)
Arun Joseph, Anand Haridass, Charles Lefurgy, Spandana Rachamalla, Sreekanth Pai, Diyanesh Chinnakkonda, Vidushi Goyal
FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware. VLSI Design (2015)
Arun Joseph, Anand Haridass, Charles Lefurgy, Sreekanth Pai, Spandana Rachamalla, Francesco Campisano
FreqLeak: A frequency step based method for efficient leakage power characterization in a system. ISLPED (2015)