Guoling Han

Publication Activity (10 Years)

Years Active: 2003-2009
Publications (10 Years): 0

Publications

Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang
Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Jason Cong, Karthik Gururaj, Guoling Han
Synthesis of reconfigurable high-performance multicore systems. FPGA (2009)
Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer
Exploring power management in multi-core systems. ASP-DAC (2008)
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman
MC-Sim: an efficient simulation tool for MPSoC designs. ICCAD (2008)
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han
Performance modeling for early analysis of multi-core systems. CODES+ISSS (2007)
Jason Cong, Guoling Han, Wei Jiang
Synthesis of an application-specific soft multiprocessor system. FPGA (2007)
Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski
Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Trans. Parallel Distributed Syst. 18 (8) (2007)
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
Platform-Based Behavior-Level and System-Level Synthesis. SoCC (2006)
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
Behavior and communication co-optimization for systems with sequential communication media. DAC (2006)
Jason Cong, Guoling Han, Zhiru Zhang
Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. IEEE Trans. Very Large Scale Integr. Syst. 14 (9) (2006)
Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
Instruction set extension with shadow registers for configurable processors. FPGA (2005)
Jason Cong, Guoling Han, Zhiru Zhang
Architecture and compilation for data bandwidth improvement in configurable embedded processors. ICCAD (2005)
Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng
Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC (2005)
Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang
Application-specific instruction generation for configurable processor architectures. FPGA (2004)
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
Architecture and synthesis for on-chip multicycle communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. ICCAD (2003)
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS (2003)