Youngsoo Shin

ORCID

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 71

Top Venues

ISCAS

ASP-DAC

DATE

ACM Trans. Design Autom. Electr. Syst.

Publications

Seunggyu Lee, Wonjae Lee, Youngsoo Shin
Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic. ACM Great Lakes Symposium on VLSI (2024)
Daijoon Hyun, Younggwang Jung, Youngsoo Shin
Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (1) (2024)
Seunggyu Lee, Daijoon Hyun, Younggwang Jung, Gangmin Cho, Youngsoo Shin
Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model. DATE (2024)
Daijoon Hyun, Younggwang Jung, Youngsoo Shin
Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs. IEEE Trans. Very Large Scale Integr. Syst. 32 (5) (2024)
Youngsoo Shin
AI-EDA: Toward a Holistic Approach to AI-Powered EDA. MLCAD (2023)
Taeyoung Kim, Gangmin Cho, Youngsoo Shin
Block-Level Power Net Routing of Analog Circuit Using Reinforcement Learning. ISCAS (2023)
Youngsoo Shin, Jungkyoon Yoon
Too Many or Too Little: Investigating Different Decision-making Experiences of Maximizers and Satisficers in HCIs. OZCHI (2023)
Daijoon Hyun, Younggwang Jung, Youngsoo Shin
Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (3) (2023)
Daijoon Hyun, Younggwang Jung, Insu Cho, Youngsoo Shin
Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs. ASP-DAC (2023)
Yoonsang Song, Gangmin Cho, Wonjae Lee, Youngsoo Shin
Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage. MLCAD (2023)
Youngsoo Shin
Lightning Talk 21: EDA with ML, Rule-Based, or Both? DAC (2023)
Daijoon Hyun, Sunwha Koh, Younggwang Jung, Taeyoung Kim, Youngsoo Shin
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking. ACM Trans. Design Autom. Electr. Syst. 28 (4) (2023)
Younggwang Jung, Daijoon Hyun, Soyoon Choi, Youngsoo Shin
Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement. ICCAD (2023)
Byungho Choi, Yonghwi Kwon, Umar Afzaal, Youngsoo Shin
Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction. ISCAS (2023)
Wonjae Lee, Insu Cho, Gangmin Cho, Youngsoo Shin
Routability-Driven Power Distribution Network Synthesis with IR-Drop Budgeting. MLCAD (2023)
Daijoon Hyun, Wonjae Lee, JinHyeong Park, Youngsoo Shin
Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells. IEEE Trans. Circuits Syst. II Express Briefs 70 (6) (2023)
Yonghwi Kwon, Youngsoo Shin
Fast Prediction of Dynamic IR-Drop Using Recurrent U-Net Architecture. MLCAD (2022)
Youngsoo Shin
Supporting Users' Decision-Making Experiences through Hyper-Personalized Human-Technology Interactions. onference on Designing Interactive Systems (Companion Volume) (2022)
Youngsoo Shin
Computational Lithography Using Machine Learning Models. IPSJ Trans. Syst. LSI Des. Methodol. 14 (2021)
Youngsoo Shin, Jungkyoon Yoon
Towards Designing Human-Centered Time Management Interfaces: The Development of 14 UX Design Guidelines for Time-related Experiences in Mobile HCI. MobileHCI (Extended Abstracts) (2021)
Sunwha Koh, Younggwang Jung, Daijoon Hyun, Youngsoo Shin
Routability Optimization for Extreme Aspect Ratio Design Using Convolutional Neural Network. ISCAS (2021)
Yonghwi Kwon, Giyoon Jung, Daijoon Hyun, Youngsoo Shin
Dynamic IR Drop Prediction Using Image-to-Image Translation Neural Network. ISCAS (2021)
Youngsoo Shin, Ruth Barankevich, Jina Lee, Saleh Kalantari
PENCODER: Design for Prospective Memory and Older Adults. CHI Extended Abstracts (2021)
Sunwha Koh, Yonghwi Kwon, Youngsoo Shin
Pre-layout clock tree estimation and optimization using artificial neural network. ISLPED (2020)
Younggwang Jung, Daijoon Hyun, Youngsoo Shin
Integrated Airgap Insertion and Layer Reassignment for Circuit Timing optimization. ASP-DAC (2020)
Wonjae Lee, Yonghwi Kwon, Youngsoo Shin
Fast ECO Leakage Optimization Using Graph Convolutional Network. ACM Great Lakes Symposium on VLSI (2020)
Daijoon Hyun, Younggwang Jung, Youngsoo Shin
Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Cheongwon Lee, Youngsoo Song, Youngsoo Shin
Endurance Enhancement of Multi-Level Cell Phase Change Memory. ICCAD (2019)
Suhyeong Choi, Seongbo Shim, Youngsoo Shin
Neural Network Classifier-Based OPC With Imbalanced Training Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (5) (2019)
Yonghwi Kwon, Inhak Han, Youngsoo Shin
Clock Gating Synthesis of Netlist with Cyclic Logic Paths. ICCAD (2019)
Youngsoo Song, Jinwook Jung, Youngsoo Shin
Standard Cell Layout Design and Placement Optimization for TFET-Based Circuits. ISCAS (2019)
Jinwook Jung, Gi-Joon Nam, Woohyun Chung, Youngsoo Shin
Integrated Latch Placement and Cloning for Timing Optimization. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Daijoon Hyun, Youngsoo Shin
Integrated Approach of Airgap Insertion for Circuit Timing Optimization. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Daijoon Hyun, Yuepeng Fan, Youngsoo Shin
Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning. DATE (2019)
Youngsoo Song, Daijoon Hyun, Jingon Lee, Jinwook Jung, Youngsoo Shin
Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning. ACM Trans. Design Autom. Electr. Syst. 24 (6) (2019)
Jingon Lee, Jinwook Jung, Youngsoo Shin
Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits. ISCAS (2018)
Joonhyuk Cho, Gangmin Cho, Youngsoo Shin
Optimization of Machine Learning Guided Optical Proximity Correction. MWSCAS (2018)
Suhyeong Choi, Seongbo Shim, Youngsoo Shin
Electrothermal Analysis With Nonconvective Boundary Conditions. IEEE Trans. Circuits Syst. II Express Briefs (8) (2018)
Kiwon Yoon, Daijoon Hyun, Youngsoo Shin
Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires. ACM Great Lakes Symposium on VLSI (2018)
Youngsoo Shin, Jinwoo Kim
Data-centered persuasion: Nudging user's prosocial behavior and designing social innovation. Comput. Hum. Behav. 80 (2018)
Youngsoo Shin
Recap of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE Des. Test 35 (3) (2018)
Daijoon Hyun, Jaewoo Seo, Youngsoo Shin
Library Optimization for Near-Threshold Voltage Design. ISCAS (2018)
Yonghwi Kwon, Jinwook Jung, Inhak Han, Youngsoo Shin
Transient Clock Power Estimation of Pre-CTS Netlist. ISCAS (2018)
Yeongmin Lee, Min-Gyu Park, Youngbae Hwang, Youngsoo Shin, Chong-Min Kyung
Memory-Efficient Parametric Semiglobal Matching. IEEE Signal Process. Lett. 25 (2) (2018)
Inhak Han, Youngsoo Shin
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. ACM Trans. Design Autom. Electr. Syst. 23 (5) (2018)
Sangmin Kim, Youngsoo Shin
Module grouping to reduce the area of test wrappers in SoCs. Integr. 60 (2018)
Daijoon Hyun, Youngsoo Shin
Automatic insertion of airgap with design rule constraints. ASP-DAC (2018)
Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (9) (2018)
Daijoon Hyun, Wachirawit Ponghiran, Youngsoo Shin
Clock tree optimization through selective airgap insertion. ISQED (2017)
Youngsoo Shin, Chaerin Im, Hyosun Oh, Jinwoo Kim
Design for experience innovation: understanding user experience in new product development. Behav. Inf. Technol. 36 (12) (2017)
Wachirawit Ponghiran, Seongbo Shim, Youngsoo Shin
Cut mask optimization for multi-patterning directed self-assembly lithography. DATE (2017)
Seongbo Shim, Woohyun Chung, Youngsoo Shin
Lithography Defect Probability and Its Application to Physical Design Optimization. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Seongbo Shim, Youngsoo Shin
Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (9) (2017)
Youngsoo Song, Jinwook Jung, Youngsoo Shin
Redundant Via insertion in SADP process with cut merging and optimization. VLSI-SoC (2017)
Youngsoo Song, Sangmin Kim, Youngsoo Shin
Timing-aware wire width optimization for SADP process. DATE (2017)
Jaewoo Seo, Jinwook Jung, Sangmin Kim, Youngsoo Shin
Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization. DAC (2017)
Youngsoo Song, Jinwook Jung, Youngsoo Shin
Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning. ACM Great Lakes Symposium on VLSI (2017)
Seongbo Shim, Youngsoo Shin
Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithography. ASP-DAC (2016)
Sangmin Kim, Seokhyeong Kang, Youngsoo Shin
Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization. ACM Trans. Design Autom. Electr. Syst. 21 (3) (2016)
Kiwon Yoon, Seongbo Shim, Youngsoo Shin
Crosslink insertion for minimizing OCV clock skew. ISCAS (2016)
Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin
OWARU: free space-aware timing-driven incremental placement. ICCAD (2016)
Seongbo Shim, Suhyeong Choi, Youngsoo Shin
Machine learning (ML)-based lithography optimizations. APCCAS (2016)
Jinwook Jung, Youngsoo Shin
Localized DNA circuit design with majority gates. BioCAS (2016)
Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin
Register grouping for synthesis of clock gating logic. ICICDT (2016)
Seongbo Shim, Woohyun Chung, Youngsoo Shin
Redundant via insertion for multiple-patterning directed-self-assembly lithography. DAC (2016)
Inhak Han, Daijoon Hyun, Youngsoo Shin
Buffer insertion to remove hold violations at multiple process corners. ASP-DAC (2016)
Kiwon Yoon, Suhyeong Choi, Youngsoo Shin
Area efficient neuromorphic circuit based on stochastic computation. ISOCC (2016)
Seongbo Shim, Woohyun Chung, Youngsoo Shin
Placement optimization for MP-DSAL compliant layout. ICICDT (2016)
Woohyun Chung, Seongbo Shim, Youngsoo Shin
Redundant via insertion in directed self-assembly lithography. DATE (2016)
Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, Youngsoo Shin
Wakeup scheduling and its buffered tree synthesis for power gating circuits. Integr. 53 (2016)
Jinwook Jung, Daijoon Hyun, Youngsoo Shin
Physical synthesis of DNA circuits with spatially localized gates. ICCD (2015)
Seongbo Shim, Jae Wook Lee, Youngsoo Shin
An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Woohyun Chung, Seongbo Shim, Youngsoo Shin
Identifying redundant inter-cell margins and its application to reducing routing congestion. DATE (2015)
Seongbo Shim, Youngsoo Shin
Physical design and mask optimization for directed self-assembly lithography (DSAL). VLSI-SoC (2015)
Youngsoo Shin, Chi-Ying Tsui
Message from the technical program chairs. VLSI-SoC (2015)
Seongbo Shim, Woohyun Chung, Youngsoo Shin
Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization. ICCAD (2015)
Youngsoo Shin, Bumho Lee, Jinwoo Kim
Prosocial Activists in SNS: The Impact of Isomorphism and Social Presence on Prosocial Behaviors. Int. J. Hum. Comput. Interact. 31 (12) (2015)
Insup Shin, Jae-Joon Kim, Youngsoo Shin
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Seongbo Shim, Yoojong Lee, Youngsoo Shin
Lithographic defect aware placement using compact standard Cells without inter-cell margin. ASP-DAC (2014)
Inhak Han, Youngsoo Shin
Simplifying Clock Gating Logic by Matching Factored Forms. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Insup Shin, Jae-Joon Kim, Youngsoo Shin
Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. ASP-DAC (2014)
Jinwook Jung, Dongsoo Lee, Youngsoo Shin
Design and Optimization of Multiple-Mesh Clock Network. VLSI-SoC (Selected Papers) (2014)
Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, Seungwhun Paik
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2014)
Seongbo Shim, Minyoung Mo, Sangmin Kim, Youngsoo Shin
Analysis and minimization of short-circuit current in mesh clock network. ICCD (2013)
Inhak Han, Youngsoo Shin
Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. ICICDT (2013)
Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
A pipeline architecture with 1-cycle timing error correction for low voltage operations. ISLPED (2013)
Sangmin Kim, Duckhwan Kim, Youngsoo Shin
Pulsed-latch ASIC synthesis in industrial design flow. ASP-DAC (2013)
Donkyu Baek, Insup Shin, Youngsoo Shin
Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. J. Circuits Syst. Comput. 22 (8) (2013)
Nam Sung Kim, Abhishek A. Sinkar, Jun Seomun, Youngsoo Shin
Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Jun Seomun, Insup Shin, Youngsoo Shin
Synthesis of Active-Mode Power-Gating Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (3) (2012)
Insup Shin, Donkyu Baek, Youngsoo Shin
Introducing irregularity to routing architecture of structured ASIC for better routability. FPT (2012)
Inhak Han, Youngsoo Shin
Synthesis of clock gating logic through factored form matching. ICICDT (2012)
Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin
Clock Gating Synthesis of Pulsed-Latch Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (7) (2012)
Donkyu Baek, Insup Shin, Youngsoo Shin
Gate delay modeling for static timing analysis of body-biased circuits. ICICDT (2012)
Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. ICCAD (2011)
Youngsoo Shin, Seungwhun Paik
Pulsed-Latch Circuits: A New Dimension in ASIC Design. IEEE Des. Test Comput. 28 (6) (2011)
Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. J. Circuits Syst. Comput. 20 (8) (2011)
Jaeha Kung, Youngsoo Shin
Compact thermal models: Assessment and pitfalls. ISOCC (2011)

Youngsoo Shin.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Youngsoo Shin