Clock Gating Synthesis of Pulsed-Latch Circuits.

Seungwhun Paik Inhak Han Sangmin Kim Youngsoo Shin

Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2012)

Keyphrases

power reduction
clock gating
power consumption
low power
power dissipation
power saving
energy efficiency
analog circuits
formal verification
logic synthesis
data center
case study
energy saving
high speed
fpga device
logic circuits
pattern recognition