Seungwhun Paik

Publication Activity (10 Years)

Years Active: 2008-2016
Publications (10 Years): 1

Top Topics

Logic Synthesis

Tree Construction

Power Dissipation

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, Youngsoo Shin
Wakeup scheduling and its buffered tree synthesis for power gating circuits. Integr. 53 (2016)
Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, Seungwhun Paik
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2014)
Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin
Clock Gating Synthesis of Pulsed-Latch Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (7) (2012)
Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. ICCAD (2011)
Youngsoo Shin, Seungwhun Paik
Pulsed-Latch Circuits: A New Dimension in ASIC Design. IEEE Des. Test Comput. 28 (6) (2011)
Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. J. Circuits Syst. Comput. 20 (8) (2011)
Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. ASP-DAC (2011)
Seungwhun Paik, Seonggwan Lee, Youngsoo Shin
Retiming Pulsed-Latch Circuits With Regulating Pulse Width. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (8) (2011)
Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin
Pulser gating: A clock gating of pulsed-latch circuits. ASP-DAC (2011)
Seungwhun Paik, Lee-eun Yu, Youngsoo Shin
Statistical time borrowing for pulsed-latch circuit designs. ASP-DAC (2010)
Jun Seomun, Seungwhun Paik, Youngsoo Shin
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. ASP-DAC (2010)
Hyein Lee, Seungwhun Paik, Youngsoo Shin
Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (3) (2010)
Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Seungwhun Paik, Sangmin Kim, Youngsoo Shin
Wakeup synthesis and its buffered tree construction for power gating circuit designs. ISLPED (2010)
Insup Shin, Seungwhun Paik, Youngsoo Shin
Register allocation for high-level synthesis using dual supply voltages. DAC (2009)
Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (3) (2009)
Seonggwan Lee, Seungwhun Paik, Youngsoo Shin
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. ICCAD (2009)
Seungwhun Paik, Insup Shin, Youngsoo Shin
HLS-l: High-level synthesis of high performance latch-based circuits. DATE (2009)
Jinseob Jeong, Seungwhun Paik, Youngsoo Shin
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. ASP-DAC (2008)
Hyein Lee, Seungwhun Paik, Youngsoo Shin
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. ICCAD (2008)
Seungwhun Paik, Youngsoo Shin
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. DAC (2008)