Insup Shin

Publication Activity (10 Years)

Years Active: 2009-2016
Publications (10 Years): 2

Top Topics

Programmable Logic

Error Correction

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Insup Shin, Jae-Joon Kim, Youngsoo Shin
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Insup Shin, Jae-Joon Kim, Youngsoo Shin
Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. ASP-DAC (2014)
Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, Seungwhun Paik
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2014)
Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
A pipeline architecture with 1-cycle timing error correction for low voltage operations. ISLPED (2013)
Donkyu Baek, Insup Shin, Youngsoo Shin
Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. J. Circuits Syst. Comput. 22 (8) (2013)
Jun Seomun, Insup Shin, Youngsoo Shin
Synthesis of Active-Mode Power-Gating Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (3) (2012)
Insup Shin, Donkyu Baek, Youngsoo Shin
Introducing irregularity to routing architecture of structured ASIC for better routability. FPT (2012)
Donkyu Baek, Insup Shin, Youngsoo Shin
Gate delay modeling for static timing analysis of body-biased circuits. ICICDT (2012)
Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. ASP-DAC (2011)
Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Jun Seomun, Insup Shin, Youngsoo Shin
Synthesis and implementation of active mode power gating circuits. DAC (2010)
Insup Shin, Seungwhun Paik, Youngsoo Shin
Register allocation for high-level synthesis using dual supply voltages. DAC (2009)
Seungwhun Paik, Insup Shin, Youngsoo Shin
HLS-l: High-level synthesis of high performance latch-based circuits. DATE (2009)