A pipeline architecture with 1-cycle timing error correction for low voltage operations.

Insup Shin Jae-Joon Kim Yu-Shiang Lin Youngsoo Shin

Published in: ISLPED (2013)

Keyphrases

error correction
low voltage
pipeline architecture
error detection
data hiding
design considerations
power line
hardware implementation
channel coding
error control
error correcting
cmos technology
error detection and correction
block codes
image processing
power management
image sequences
dynamic range