Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling.
Insup ShinJae-Joon KimYoungsoo ShinPublished in: ASP-DAC (2014)
Keyphrases
- error correction
- pipeline architecture
- power losses
- error detection
- data hiding
- hardware implementation
- duty cycle
- channel coding
- error correcting
- power consumption
- error analysis
- reactive power
- electrical power
- error control
- single phase
- power quality
- watermarking scheme
- block codes
- power system
- ldpc codes
- computer simulation
- error detection and correction
- reed solomon
- pattern recognition
- fault tolerant
- barcode