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Umar Afzaal
ORCID
Publication Activity (10 Years)
Years Active: 2017-2023
Publications (10 Years): 9
Top Topics
Hardware Architecture
Power Reduction
Software Implementation
Delay Insensitive
Top Venues
DSD
ICTC
IEEE Trans. Evol. Comput.
FPL
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Publications
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Umar Afzaal
,
Abdus Sami Hassan
,
Muhammad Usman
,
Jeong-A Lee
On the Evolutionary Synthesis of Fault-Resilient Digital Circuits.
IEEE Trans. Evol. Comput.
27 (2) (2023)
Byungho Choi
,
Yonghwi Kwon
,
Umar Afzaal
,
Youngsoo Shin
Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction.
ISCAS
(2023)
Umar Afzaal
,
Jeong-A Lee
Trading the Reliability of Approximate TMR in FPGAs with the Cost of Mitigation.
DSD
(2020)
Umar Afzaal
,
Jeong-A Lee
Low-cost Hardware Redundancy for Fault-mitigation in Power-constrained IoT Systems.
ICTC
(2020)
Umar Afzaal
,
Abdus Sami Hassan
,
Jeong-A Lee
Improved error detection performance of logic implication checking in FPGA circuits.
Microprocess. Microsystems
78 (2020)
Inayat Ullah
,
Zahid Ullah
,
Umar Afzaal
,
Jeong-A Lee
DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates.
IEEE Trans. Very Large Scale Integr. Syst.
27 (6) (2019)
Umar Afzaal
,
Abdus Sami Hassan
,
Tooba Arifeen
,
Jeong-A Lee
Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking.
DSD
(2018)
Inayat Ullah
,
Umar Afzaal
,
Zahid Ullah
,
Jeong-A Lee
High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGA.
DSD
(2018)
Umar Afzaal
,
Jeong-A Lee
FPGA-based design of a self-checking TMR voter.
FPL
(2017)