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Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels.

Victor V. ZyubanPhilip N. Strenski
Published in: ISLPED (2002)
Keyphrases
  • power consumption
  • single phase
  • high speed
  • levels of abstraction
  • duty cycle
  • design methodology
  • power reduction
  • chip design
  • multi agent
  • higher level
  • low power
  • lower level
  • power dissipation
  • logic synthesis