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A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.
John Barth
Don Plass
Erik Nelson
Charlie Hwang
Gregory Fredeman
Michael A. Sperling
Abraham Mathews
William R. Reohr
Kavita Nair
N. Cao
Published in:
ISSCC (2010)
Keyphrases
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silicon on insulator
dynamic random access memory
ibm power processor
cmos technology
embedded dram
memory subsystem
error resilience
power management
instruction set
power consumption
low power
ibm zenterprise
image sensor
power dissipation
low voltage
digital camera
parallel processing