Steve Lamphier

Publication Activity (10 Years)

Years Active: 2000-2013
Publications (10 Years): 0

Top Topics

Protein Folding

Fine Granularity

Ibm Power Processor

Top Venues

Publications

Harold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad Imran Younus
A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction. ISSCC (2013)
Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. IEEE J. Solid State Circuits 47 (1) (2012)
Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens
A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. ISSCC (2011)
Vinod Ramadurai, Harold Pilo, John Andersen, Geordie Braceras, John Gabric, Daniel Geise, Steve Lamphier, Yue Tan
An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management. IEEE J. Solid State Circuits 44 (1) (2009)
Harold Pilo, Vaidyanathan Ramadurai, Geordie Braceras, John Gabric, Steve Lamphier, Yue Tan
A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management. ISSCC (2008)
Larry Wissel, Harold Pilo, Chris LeBlanc, Xiaopeng Wang, Steve Lamphier, Michael Fragano
A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology. CICC (2007)
Harold Pilo, Charlie Barwin, Geordie Braceras, Chris Browning, Steve Lamphier, Fred Towler
An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage. IEEE J. Solid State Circuits 42 (4) (2007)
Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits 38 (11) (2003)
Harold Pilo, Stu Hall, Patrick Hansen, Steve Lamphier, Chris Murphy
Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond. ITC (2000)
Harold Pilo, Archie Allen, Jim Covino, Patrick Hansen, Steve Lamphier, Chris Murphy, Terry Traver, Pui Yee
An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin. IEEE J. Solid State Circuits 35 (11) (2000)