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An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage.
Harold Pilo
Charlie Barwin
Geordie Braceras
Chris Browning
Steve Lamphier
Fred Towler
Published in:
IEEE J. Solid State Circuits (2007)
Keyphrases
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power consumption
nm technology
power dissipation
clock gating
low power
cmos technology
design process
power reduction
high level synthesis
signal processing
real time
high speed
power system
low cost
analog circuits
logic circuits
low voltage
image processing