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A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology.
Larry Wissel
Harold Pilo
Chris LeBlanc
Xiaopeng Wang
Steve Lamphier
Michael Fragano
Published in:
CICC (2007)
Keyphrases
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cmos technology
low power
power consumption
spl times
low voltage
parallel processing
power dissipation
high speed
image sensor
mixed signal
silicon on insulator
low cost
random access
embedded dram
digital signal processing
hardware implementation
computer vision