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An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management.

Vinod RamaduraiHarold PiloJohn AndersenGeordie BracerasJohn GabricDaniel GeiseSteve LamphierYue Tan
Published in: IEEE J. Solid State Circuits (2009)
Keyphrases
  • power consumption
  • dynamic power management
  • power management
  • silicon on insulator
  • sensor networks
  • low power
  • database
  • databases
  • artificial intelligence
  • data collection
  • times faster
  • cmos technology
  • power reduction