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A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface.
Harold Pilo
Darren Anand
John Barth
Steve Burns
Phil Corson
Jim Covino
Steve Lamphier
Published in:
IEEE J. Solid State Circuits (2003)
Keyphrases
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dynamic random access memory
user interface
high density
user friendly
low voltage
main memory
high speed
power consumption
times faster
wireless sensor networks
low power
network simulator
query interface
random access memory