Darren Anand

Publication Activity (10 Years)

Years Active: 2001-2019
Publications (10 Years): 2

Top Topics

Modeling Language

Computing Power

Top Venues

Publications

Eric Hunt-Schroeder, Darren Anand, Edward Hwang, Aaron Cummings, Matthew Deming, Michael Roberge, Michael Ziegerhofer
Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory. NATW (2019)
Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata
14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming. VLSI Circuits (2018)
Darren Anand, Kevin W. Gorman, Mark Jacunski, Adrian Paparelli
Embedded DRAM in 45-nm Technology and Beyond. IEEE Des. Test Comput. 28 (1) (2011)
Mark Jacunski, Darren Anand, Robert Busch, John A. Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. CICC (2010)
Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. CICC (2007)
Kevin W. Gorman, Darren Anand, Gary Pomichter, William R. Corbin
Low Cost Test of High Bandwidth Embedded Memories. CICC (2006)
John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits 40 (1) (2005)
Michael R. Nelms, Kevin W. Gorman, Darren Anand
Generating At-Speed Array Fail Maps with Low-Speed ATE. VTS (2004)
Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater
An On-Chip Self-Repair Calculation and Fusing Methodology. IEEE Des. Test Comput. 20 (5) (2003)
Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits 38 (11) (2003)
John E. Barth Jr., Jeffrey H. Dreibelbis, Eric A. Nelson, Darren Anand, Gary Pomichter, Peter Jakobsen, Michael R. Nelms, Jeffrey Leach, George M. Belansek
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. IBM J. Res. Dev. 46 (6) (2002)
Michael R. Ouellette, Darren Anand, Peter Jakobsen
Shared fuse macro for multiple embedded memory devices with redundancy. CICC (2001)
Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek
Embedded DRAM built in self test and methodology for test insertion. ITC (2001)